In the typical process of manufacturing quad no-lead frame (QFN) or thin QFN (TQFN) integrated circuit (IC) packages, an array of supported semiconductor dies are electrically connected to a common lead frame, and are commonly encapsulated by an injection molded compound. Then, the encapsulated structure undergoes a singulation process where the structure is diced up in order to form individual IC packages, each encapsulating a corresponding semiconductor die and other related elements. As discussed in more detail below, the singulation process results in an unprotected side of the package terminals to be exposed to the environment. As a consequence, oxides may form on the terminal sides, which may lead to poor solderability of the IC terminals during subsequent assembly of the IC package onto a printed circuit board (PCB). This is better explained with reference to the following example.
FIG. 1A illustrates a transparent front view of an array 100 of exemplary QFN IC packages prior to the singulation manufacturing step. In this example, only two (2) adjacent QFN packages 101-1 and 101-2 are shown for ease of explanation. Each QFN package (101-1 or 101-2) may comprise a semiconductor die (104-1 or 104-2) securely disposed on a thermal pad (110-1 or 110-2) by way of an adhesive layer (108-1 or 108-2). Each semiconductor die (104-1 or 104-2) includes contact pads (106-1 or 106-2) electrically coupled to a copper (Cu) lead frame 120 by way of respective wirebonds (112-1 or 112-2). In the integrated array 100, the contact pads of adjacent semiconductor dies electrically connect, via the corresponding wirebonds, to the same terminal of the lead frame 120. Prior to singulation, a thin coating of solderable plating 130 (e.g., a Sn-based plating) is formed on the underside of each of the terminal of the lead frame 120 using, for example, an electroplating process. During singulation, the array 100 is diced up along a substantially vertical line at the midpoint between adjacent QFN packages, as illustrated by the dashed cut lines. The cutting of the array 100 may be performed using a stamping or sawing tool.
FIG. 1B illustrates a transparent front view of the exemplary QFN IC package 101-1 after completion of the singulation manufacturing step. As noted, the underside of the terminal 120-1 of the QFN IC package 101-1 is substantially covered by the solderable coating 130-1 disposed thereon. This protects the underside of the terminal 120-1 against oxidation due to aging and/or subsequent processing of the QFN IC package 101-1. However, the solderable coating 130-1 is not present on the sides of the terminals 120-1, where the cutting or separation of the individual QFN IC packages occurred. Accordingly, the sides of the terminals 120-1 are not protected from oxidation due to aging and subsequent processing. Thus, the sides of the terminals 120-1 are susceptible to oxidation and exposure to other contaminates. The side surfaces 122-1 of the terminals 120-1 are represented by a dotted shading in order to represent the oxidized and contaminated surfaces, as best shown in FIG. 1C. Such surfaces generally have poor solderability properties, which may make the assembly of the QFN package onto a PCB difficult and unreliable. The poor solderability properties may result in the formation of solder balls and other defects formed on the side terminals of the IC package.